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Technical Discussions
This is a technical discussion area for technical issues relating to Linux Itanium. You may also choose to participate in these discussions via email. The Gelato Federation claims no responsibility for the accuracy of items posted here. See our Terms of Service for more information.
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EPIC8 Call for Papers (Toronto, Canada, April 24th, 2010)
2009.12.08- Posted by Andrey Bokhanko |  Post a comment
CALL FOR PAPERS
===============
Eighth Workshop on Explicitly Parallel Instruction
Computing Architectures and Compiler Technology (EPIC-8)
April 24, 2010
Toronto, Canada
www.cgo.org/cgo2010/epic8/
In conjunction with the IEEE/ACM International Symposium
on Code Generation and Optimization (CGO)
Researchers from both academia and industry are invited to share their
latest research findings in the area of EPIC architectures and compiler
technology. The EPIC style of architecture was developed to enable new
levels of instruction-level parallelism not achieved with traditional
architectures. By allowing the compiler to express program parallelism
and other relevant information directly to the processor, EPIC
architectures can overcome hardware complexity issues that limit
performance in traditional microprocessors.
The major challenge in realizing the full potential of EPIC architectures
is developing compiler and runtime optimization technologies that
effectively deploy explicitly defined hardware mechanisms, and deliver
performance for both commercial and scientific applications. This
workshop will focus on promising research concepts that enable the EPIC
architecture model.
TOPICS OF INTEREST
Topics of interest include, but are not limited to:
Compiler Optimizations:
- Instruction scheduling, software pipelining, predication,
control and data speculation, register allocation
- Thread-level parallelization
- Versioning approaches to dynamically adapt to runtime behavior
- Techniques to mitigate in-order memory stalls, like prefetching,
helper threads, and load clustering
- Compiler-directed memory-hierarchy and cache-coherency management
- Methods of program analysis and verification that are related to EPIC
- Higher-level optimizations that are related to EPIC
- Validation of compiler optimizations
Binary Translation:
- Methods of binary translation applicable to EPIC architectures
- Hardware support of binary translation
Feedback-Directed Optimizations:
- Especially performance monitoring unit (PMU) driven optimizations
- Dynamic optimizations
Microarchitecture:
- Novel architectures and microarchitectures
- In-order versus out-of-order designs, hybrid approaches
- Multi-threaded and multi-core EPIC architectures
- Power and energy aware computing techniques for EPIC machines
Advanced Uses of EPIC Architectures:
- Virtualization and Secure Computing
- Special purpose applications
Performance Analysis of EPIC Architectures:
- Commercial and scientific workload studies for EPIC models
- Effects of architectural features on workload behavior
- Experimental evaluation of Itanium microprocessors
- Performance comparisons with other architectures
- Tools for analysis, instrumentation, and architecture experiments
CHAIR
Andrey Bokhanko, Intel
andrey.s.bokhanko@intel.com
IMPORTANT DATES
**** SUBMISSION DEADLINE: Monday, February 15, 2010 ****
Acceptances Mailed: February 22, 2010
Final Version Due: April 2, 2010
Workshop Date: April 24, 2010 (half day workshop)
SUBMISSION GUIDELINES
Full papers of up to 22 pages or extended abstracts of up to 8 pages
can be submitted (8.5"x11" double-spaced pages, using 11pt or larger
font). Clearly describe the nature of the work, its significance and
the current status of the research. Include a title page containing
the title of the paper, list of authors and their affiliations,
addresses, telephone and fax numbers, email addresses and the name
of the corresponding author. papers will be published on EPIC-8
web-site (the copyright will remain with the author).
Storage device with SuSE Linux on an HP Itanium
rx7620 ia64 server.
2009.11.06- Posted by Jesse Dougherty | 2 comments
Let me start by saying, I'm a sales person with limited knowledge of
Linux. We mainly sell HP / HP-UX related hardware.
I need to find a storage array that is supported under SuSE Linux. The
host server is an HP Itanium ia64 type server. I need to have about 5TB
of storage.
Can anyone point me to a storage array that will be compatible with the
above hardware and OS?
Thanks
Jesse
Cypress Technology Inc
Running big-endian processes on little-endian RHEL IA64
2009.06.24- Posted by Andrew Paprocki | Post a comment
I've been reading that it is possible to flip a process into big-endian mode from user-space by setting the 'be' bit of the PSR register using the 'sum' (Set User Mask) instruction.
Has anyone else tried this and had success running code built to perform big-endian data access on a RHEL or SUSE system?
Radeon 9800 on a zx2000?
2009.06.24- Posted by Michael Brown | Post a comment
Hello all,
I'm currently running a zx2000 with a Radeon 7000. I also have a spare Radeon 9800, which is basically a Radeon 9700, which is basically a FireGL X1 :) Apparently the X1/Z1's that are sold with the zx2000 are standard cards, with the EFI firmware simulating a x86 BIOS during EFI boot. So the first thing I tried was just plugging the card in. No dice - MCA during the EFI video initialization phase (accessing address 0xB8000, the start of the video memory buffer).
Being the optimistic person I am, I forced HP's Z1 BIOS (since the X1 BIOS is for 256 MB cards) onto the card, and tested it on a standard x86 PC. Booted fine, went into Windows fine, no obvious ill effects. However - putting the card into the zx2000 did not work at all. One of two things happens. The first is that PCI bus enumeration falls over (out of resources, or "unknown error"), in which case Linux (still thinking a card exists, for some reason) causes a MCA when it tries to write to the screen area right at the start of the boot process.
However, sometimes (I don't know why there's a difference) the PCI bus enumeration works fine. In these cases, the EFI does the BIOS emulation thing, and falls over helf way through with a MCA (again 0xb8000). This seems odd to me - the r300 and r350 are very similar, the firmware works correctly on this card in an x86 box, and the firmware (presumably) works on a HP-original Z1 in the zx2000.
I tried to manually kick the card into life when it didn't die during EFI initialization. While I can write to the PCI configuration space and set up the BARs to map the space into the address 0x80000000, I still get a MCA when I try to read from this space. I tried tweaking the zx1 and Mercury configuration to forward additional space to rope 0 (it normally only gets 512 MB from the two distributed allocations, the card wants 768 MB for some reason, so I moved the directed allocation of the rope 2 and 3 space to go to rope 0) but this didn't seem to help things.
So, am I bashing my head against a wall here? Were the X1/Z1 cards that went out with the zx2000's special in some way? Or alternatively, is it possible to tell EFI not to try and initialize the card, and leave that the X which can at least be debugged?
new Itanium blog
2009.04.20- Posted by Mark K. Smith | Post a comment
Dear Gelato Community,
The Itanium Solutions Alliance has launched a new Itanium blog:
blog.itaniumsolutions.org ISA is eager to build out their roster of
bloggers, generate regular posts, establish links throughout the
blogosphere, and eventually develop this into the principal forum for
Itanium on the web. If you are interested in blogging about any topic
related to Linux on Itanium, please contact Brandon Wick
.
All the best,
Mark
\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_
Mark K. Smith, Managing Director
The Gelato Federation
mksmith@gelato.org, (217) 244-2882
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