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- What is Gelato?
- The global
technical community dedicated to advancing Linux® on the Intel®
Itanium® platform through collaboration, education, and leadership.
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Housed at the University of Houston, the Texas Learning and
Computation Center (TLC2) serves as a campus-wide center to foster and
support multidisciplinary research, education, and training in the
computational sciences, computer science, and information technology.- Learn More
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Technical Discussions
This is a technical discussion area for technical issues relating to Linux Itanium. You may also choose to participate in these discussions via email. The Gelato Federation claims no responsibility for the accuracy of items posted here. See our Terms of Service for more information.
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new Itanium blog
2009.04.20- Posted by Mark K. Smith |  Post a comment
Dear Gelato Community,
The Itanium Solutions Alliance has launched a new Itanium blog:
blog.itaniumsolutions.org ISA is eager to build out their roster of
bloggers, generate regular posts, establish links throughout the
blogosphere, and eventually develop this into the principal forum for
Itanium on the web. If you are interested in blogging about any topic
related to Linux on Itanium, please contact Brandon Wick
.
All the best,
Mark
\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_
Mark K. Smith, Managing Director
The Gelato Federation
mksmith@gelato.org, (217) 244-2882
Announcement: a new forum dedicated to Intel development tools for Itanium
2009.04.16- Posted by Andrey Bokhanko | Post a comment
Hi All,
This is to let you know that a new forum dedicated to Intel development tools for Itanium architecture went live.
software.intel.com/en-us/forums/intel-so
You are welcome to visit, ask questions and contribute!
how to support inline assembly in Openimpact
2008.11.05- Posted by josefina | 1 comment
I'm now porting impact to our platform, but impact cann't support inline assebly, is there any other way to support inline assembly?
HP zx6000 question: what faster cpus can be installed
2005.10.28- Posted by tony | 10 comments
Hi.
I have a HP zx6000 with 2x 900mhz CPU. Looking to upgrade
the cpus.
Is this a complete list of the Itanium2 chips released?
www.cpu-world.com/sspec/Itanium%202.html
I believe I'm limited to 400mhz bus speeds but I wasn't sure if a 1.8ghz part had been released?
As far as the 1.6ghz is concerned (from the above) it looks like it was available in:
3mb cache (2 steppings) SL7EC SL7FQ
6mb cache SL7EB
9mb cache SL87H
Are all of these compatible with the zx6000? Any steppings problematic defect wise? Is specific HP packaging required or are all of the chips (from any hardware vendor, say bought of eBay) compatible?
URL pointers welcomed.
BE_L1D_FPU_BUBBLE_L1D_L2BPRESS
2009.03.06- Posted by Chabachull | Post a comment
Marc said:
IIRC, I should look at 3 problems:
BE_L1D_FPU_BUBBLE_L1D
BE_L1D_FPU_BUBBLE_L1D_L2BPRESS
BE_L1D_FPU_BUBBLE_L1D_DCURECIR
because all three events are responsible for BE_L1D_FPU_BUBBLE_ALL
stalls, is that correct?
Why is there only mention of L1, don't FP load bypass L1? Can't L2
misses stall the pipeline?
To give a small view of this: yes the FP bypass L1D cache but it has nevertheless some effect on it.
Let me explain:
To schematize, at the entry of the L2D cache, there is a Buffer (or queue) receiving the requests. Eventually, due to recirculating requests, the queue can be full. Then, there is a hardware mecanism to send a "message" to the L1D to stop it sending request to the full buffer.
The counter BE_L1D_FPU_BUBBLE_L1D_L2BPRESS measures these messages.
So even if the FP bypass the L1D cache, when the buffer is full, the L1D is somehow put in action due to a too large amount of FP operations.
I hope I have been of some help in this matter.
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