About
As Moore's Law evolves into Moore's Core, most hardware vendors are faced with the new reality of stagnant single processor-core performance, and the efficient utilization of many parallel streams. This performance brick wall, and the need to effectively use multi-cores, will hit every computer user, and not just the bleeding edge! However, the software environment for multi-core support is still in its infancy, and hereby presents a major opportunity for researchers of languages, tools and systems support. This problem is further exacerbated by the numerous accelerators bursting onto the high-end stage. The goal of this workshop is to provide a forum for understanding and discussing the software solutions that are required to make multi-core systems a success, both in terms of usability and performance.
Current programming models for shared-memory multi-processors by using threads and locks are not very user-friendly. Problems with synchronization overhead and indeterminancy can become prohibitive to the most experienced programmers. However, rich support in languages, compilers and run-time tools can alleviate the pain, and help users do a much better job of using parallelism through better debugging, tuning and understanding of the workload.
Furthermore, the transactional memory model of programming reduces the burden on the user to deal directly with consistency, and transfers much of that responsibility to the underlying compiler and run-time libraries. Similarly, incorporation of high-level parallel libraries is also a level of abstraction that can help users utilize parallelism while programming with sequential semantics. One of the objectives of this workshop is to explore the abstractions that are most meaningful and valuable without sacrificing application performance.
Hybrid multi-core architectures (accelerators) are becoming popular, thus providing another dimension to the multi-core revolution, and opening up potentials for huge performance gains in certain applications. NVIDIA and ATI hardware are already available, and soon may be available on personal computers. The challenge is to provide a programming environment where users do not need to know all the internal details but can port their applications to different hardware configurations in a seamless manner. Another objective of this workshop is to identify the classes of applications that would benefit the most from such hybrid multi-cores while exploring ways to extend these systems and software for more general purpose parallel programming.
Topics of interest include, but are not limited to:
- Multi-threading and associated debugging and performance analysis tools
- Compilers and run-time systems
- Programming models
- Transactional memory
- Parallel libraries
- Performance analysis, debugging, and tuning tools
- Workload characterization
- Heterogeneous multi-core systems
- RAS with 100+ cores
- How to manage and take advantage of a Non-Uniform Core CPU